Analog-to-digital converters (ADCs) form a critical interface in electronic systems, enabling the discrete-time digital processing of continuous-time analog signals. The selection of an ADC for a specific application typically hinges on parameters such as sampling rate and effective number of bits (ENOB), which dictate the quantization noise. A fundamental assumption in conventional ADC operation is that the input signal's dynamic range (DR) is contained within the ADC's input range to avoid non-linear distortion due to saturation (clipping). However, high-DR signals necessitate high-DR (HDR) ADCs, leading to increased power consumption and higher bit-resolution requirements to maintain a desired signal-to-quantization-noise ratio. In recent years, modulo-folding-based ADC architectures have emerged as a compelling alternative for digitizing high-DR signals using a low-DR ADC preceded by a non-linear modulo operation. This folding process maps the input signal into a smaller range, effectively preventing clipping. Subsequently, a digital unfolding algorithm is required to reconstruct the original signal from its folded representation. The performance of such systems is intricately linked to the co-design of the modulo-folding circuit and the unfolding algorithm. While significant research has focused on the development and analysis of these unfolding techniques, their applications, and hardware implementations, a comprehensive understanding of their power efficiency compared to conventional HDR-ADCs and their connections to established sampling paradigms remains relatively underexplored. This talk will adopt a tutorial approach, systematically introducing the principles of modulo-folding ADCs. We will delve into the mathematical framework of the folding operation and elucidate the functionality of various unfolding algorithms. Furthermore, we will explore the relationship between this novel sampling scheme and classical techniques such as delta modulation (DM) and sigma-delta modulation, highlighting potential synergies and distinctions. We will also discuss practical hardware considerations and analyze the power consumption trade-offs associated with modulo-folding ADCs. Finally, we will present a case study involving the application of this approach to a linear digital communication problem, showcasing its potential benefits and limitations through quantitative results.
Received the B.Eng. degree from the Electronics and Communication Engineering Department, Jalpaiguri Government Engineering College, India, in 2005, and the M.Eng. degree in electrical engineering from the Department of Electrical Engineering, Indian Institute of Technology Kanpur, India, in 2009. Subsequently, he worked as a Researcher with the Indian Space Research Organization (ISRO), India, and Tata Consultancy Services (TCS) Innovation Labs, Mumbai, India. In 2011, he joined the Spectrum Lab, Department of Electrical Engineering, Indian Institute of Science, Bangalore, for his Ph.D. From 2017 to 2021, he was a Postdoctoral Fellow with the Department of Electrical Engineering, Technion - Israel Institute of Technology, and Mathematics and Computer Science, Weizmann Institute of Science, Israel. Currently, he is an assistant professor at the Department of Electrical Engineering, Indian Institute of Technology (IIT) Bombay, India. His research interests include sampling theory, particularly finite-rate-of-innovation signal sampling, compressive sensing, machine learning, blind deconvolution, sparse array signal processing, and spectral estimation.